patch-2.3.48 linux/arch/mips/mm/r4xx0.c

• Lines: 696
• Date: Thu Feb 24 22:52:30 2000
• Orig file: v2.3.47/linux/arch/mips/mm/r4xx0.c
• Orig date: Tue Aug 31 17:29:12 1999

diff -u --recursive --new-file v2.3.47/linux/arch/mips/mm/r4xx0.c linux/arch/mips/mm/r4xx0.c
@@ -1,4 +1,4 @@
-/* $Id: r4xx0.c,v 1.22 1999/06/17 13:25:51 ralf Exp $
+/* $Id: r4xx0.c,v 1.30 2000/02/24 01:12:37 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -22,13 +22,10 @@
 
 #include <asm/bcache.h>
 #include <asm/io.h>
-#include <asm/sgi.h>
-#include <asm/sgimc.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/bootinfo.h>
-#include <asm/sgialib.h>
 #include <asm/mmu_context.h>
 
 /* CP0 hazard avoidance. */
@@ -81,7 +78,7 @@
  *   versions of R4000 and R4400.
  */
 
-static void r4k_clear_page_d16(unsigned long page)
+static void r4k_clear_page_d16(void * page)
 {
 	__asm__ __volatile__(
 		".set\tnoreorder\n\t"
@@ -112,7 +109,7 @@
 		:"$1","memory");
 }
 
-static void r4k_clear_page_d32(unsigned long page)
+static void r4k_clear_page_d32(void * page)
 {
 	__asm__ __volatile__(
 		".set\tnoreorder\n\t"
@@ -169,7 +166,7 @@
  *                              nop
  *                              cache       Hit_Writeback_Invalidate_D
  */
-static void r4k_clear_page_r4600_v1(unsigned long page)
+static void r4k_clear_page_r4600_v1(void * page)
 {
 	__asm__ __volatile__(
 		".set\tnoreorder\n\t"
@@ -208,7 +205,7 @@
 /*
  * And this one is for the R4600 V2.0
  */
-static void r4k_clear_page_r4600_v2(unsigned long page)
+static void r4k_clear_page_r4600_v2(void * page)
 {
 	unsigned int flags;
 
@@ -251,7 +248,7 @@
  * this the kernel crashed shortly after mounting the root filesystem.  CPU
  * bug?  Weirdo cache instruction semantics?
  */
-static void r4k_clear_page_s16(unsigned long page)
+static void r4k_clear_page_s16(void * page)
 {
 	__asm__ __volatile__(
 		".set\tnoreorder\n\t"
@@ -282,7 +279,7 @@
 		:"$1","memory");
 }
 
-static void r4k_clear_page_s32(unsigned long page)
+static void r4k_clear_page_s32(void * page)
 {
 	__asm__ __volatile__(
 		".set\tnoreorder\n\t"
@@ -311,7 +308,7 @@
 		:"$1","memory");
 }
 
-static void r4k_clear_page_s64(unsigned long page)
+static void r4k_clear_page_s64(void * page)
 {
 	__asm__ __volatile__(
 		".set\tnoreorder\n\t"
@@ -339,7 +336,7 @@
 		:"$1","memory");
 }
 
-static void r4k_clear_page_s128(unsigned long page)
+static void r4k_clear_page_s128(void * page)
 {
 	__asm__ __volatile__(
 		".set\tnoreorder\n\t"
@@ -381,7 +378,7 @@
  * virtual address where the copy will be accessed.
  */
 
-static void r4k_copy_page_d16(unsigned long to, unsigned long from)
+static void r4k_copy_page_d16(void * to, void * from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -440,7 +437,7 @@
 		 "i" (Create_Dirty_Excl_D));
 }
 
-static void r4k_copy_page_d32(unsigned long to, unsigned long from)
+static void r4k_copy_page_d32(void * to, void * from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -500,7 +497,7 @@
 /*
  * Again a special version for the R4600 V1.x
  */
-static void r4k_copy_page_r4600_v1(unsigned long to, unsigned long from)
+static void r4k_copy_page_r4600_v1(void * to, void * from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -565,7 +562,7 @@
 		 "i" (Create_Dirty_Excl_D));
 }
 
-static void r4k_copy_page_r4600_v2(unsigned long to, unsigned long from)
+static void r4k_copy_page_r4600_v2(void * to, void * from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -636,7 +633,7 @@
 /*
  * These are for R4000SC / R4400MC
  */
-static void r4k_copy_page_s16(unsigned long to, unsigned long from)
+static void r4k_copy_page_s16(void * to, void * from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -695,7 +692,7 @@
 		 "i" (Create_Dirty_Excl_SD));
 }
 
-static void r4k_copy_page_s32(unsigned long to, unsigned long from)
+static void r4k_copy_page_s32(void * to, void * from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -752,7 +749,7 @@
 		 "i" (Create_Dirty_Excl_SD));
 }
 
-static void r4k_copy_page_s64(unsigned long to, unsigned long from)
+static void r4k_copy_page_s64(void * to, void * from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -808,7 +805,7 @@
 		 "i" (Create_Dirty_Excl_SD));
 }
 
-static void r4k_copy_page_s128(unsigned long to, unsigned long from)
+static void r4k_copy_page_s128(void * to, void * from)
 {
 	unsigned long dummy1, dummy2;
 	unsigned long reg1, reg2, reg3, reg4;
@@ -1742,7 +1739,7 @@
 	 * If ownes no valid ASID yet, cannot possibly have gotten
 	 * this page into the cache.
 	 */
-	if(mm->context == 0)
+	if (mm->context == 0)
 		return;
 
 #ifdef DEBUG_CACHE
@@ -1926,7 +1923,7 @@
 	 * If the page isn't marked valid, the page cannot possibly be
 	 * in the cache.
 	 */
-	if(!(pte_val(*ptep) & _PAGE_PRESENT))
+	if (!(pte_val(*ptep) & _PAGE_PRESENT))
 		goto out;
 
 	text = (vma->vm_flags & VM_EXEC);
@@ -1936,7 +1933,7 @@
 	 * for every cache flush operation.  So we do indexed flushes
 	 * in that case, which doesn't overly flush the cache too much.
 	 */
-	if((mm == current->mm) && (pte_val(*ptep) & _PAGE_VALID)) {
+	if((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 		blast_dcache32_page(page);
 		if(text)
 			blast_icache32_page(page);
@@ -1965,110 +1962,119 @@
  *    flush.
  * 3) In KSEG1, no flush necessary.
  */
-static void r4k_flush_page_to_ram_s16d16i16(unsigned long page)
+static void r4k_flush_page_to_ram_s16d16i16(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		blast_scache16_page(page);
+		blast_scache16_page(addr);
 	}
 }
 
-static void r4k_flush_page_to_ram_s32d16i16(unsigned long page)
+static void r4k_flush_page_to_ram_s32d16i16(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		blast_scache32_page(page);
+		blast_scache32_page(addr);
 	}
 }
 
-static void r4k_flush_page_to_ram_s64d16i16(unsigned long page)
+static void r4k_flush_page_to_ram_s64d16i16(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		blast_scache64_page(page);
+		blast_scache64_page(addr);
 	}
 }
 
-static void r4k_flush_page_to_ram_s128d16i16(unsigned long page)
+static void r4k_flush_page_to_ram_s128d16i16(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		blast_scache128_page(page);
+		blast_scache128_page(addr);
 	}
 }
 
-static void r4k_flush_page_to_ram_s32d32i32(unsigned long page)
+static void r4k_flush_page_to_ram_s32d32i32(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		blast_scache32_page(page);
+		blast_scache32_page(addr);
 	}
 }
 
-static void r4k_flush_page_to_ram_s64d32i32(unsigned long page)
+static void r4k_flush_page_to_ram_s64d32i32(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		blast_scache64_page(page);
+		blast_scache64_page(addr);
 	}
 }
 
-static void r4k_flush_page_to_ram_s128d32i32(unsigned long page)
+static void r4k_flush_page_to_ram_s128d32i32(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		blast_scache128_page(page);
+		blast_scache128_page(addr);
 	}
 }
 
-static void r4k_flush_page_to_ram_d16i16(unsigned long page)
+static void r4k_flush_page_to_ram_d16i16(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 		unsigned long flags;
 
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		save_and_cli(flags);
-		blast_dcache16_page(page);
-		restore_flags(flags);
+		__save_and_cli(flags);
+		blast_dcache16_page(addr);
+		__restore_flags(flags);
 	}
 }
 
-static void r4k_flush_page_to_ram_d32i32(unsigned long page)
+static void r4k_flush_page_to_ram_d32i32(struct page * page)
 {
-	page &= PAGE_MASK;
-	if((page >= KSEG0 && page < KSEG1) || (page >= KSEG2)) {
+	unsigned long addr = page_address(page) & PAGE_MASK;
+
+	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
 		unsigned long flags;
 
 #ifdef DEBUG_CACHE
-		printk("cram[%08lx]", page);
+		printk("cram[%08lx]", addr);
 #endif
-		save_and_cli(flags);
-		blast_dcache32_page(page);
-		restore_flags(flags);
+		__save_and_cli(flags);
+		blast_dcache32_page(addr);
+		__restore_flags(flags);
 	}
 }
 
@@ -2202,7 +2208,7 @@
 	unsigned int flags;
 
 	daddr = addr & ~(dc_lsize - 1);
-	save_and_cli(flags);
+	__save_and_cli(flags);
 
 	/* Clear internal cache refill buffer */
 	*(volatile unsigned int *)KSEG1;
@@ -2212,7 +2218,7 @@
 	iaddr = addr & ~(ic_lsize - 1);
 	protected_flush_icache_line(iaddr);
 	protected_flush_icache_line(iaddr + ic_lsize);
-	restore_flags(flags);
+	__restore_flags(flags);
 }
 
 #undef DEBUG_TLB
@@ -2222,7 +2228,7 @@
 
 #define NTLB_ENTRIES_HALF  24  /* Fixed on all R4XX0 variants... */
 
-static inline void r4k_flush_tlb_all(void)
+void flush_tlb_all(void)
 {
 	unsigned long flags;
 	unsigned long old_ctx;
@@ -2255,7 +2261,7 @@
 	restore_flags(flags);
 }
 
-static void r4k_flush_tlb_mm(struct mm_struct *mm)
+void flush_tlb_mm(struct mm_struct *mm)
 {
 	if(mm->context != 0) {
 		unsigned long flags;
@@ -2271,7 +2277,7 @@
 	}
 }
 
-static void r4k_flush_tlb_range(struct mm_struct *mm, unsigned long start,
+void flush_tlb_range(struct mm_struct *mm, unsigned long start,
 				unsigned long end)
 {
 	if(mm->context != 0) {
@@ -2320,7 +2326,7 @@
 	}
 }
 
-static void r4k_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 {
 	if(vma->vm_mm->context != 0) {
 		unsigned long flags;
@@ -2354,11 +2360,11 @@
 }
 
 /* Load a new root pointer into the TLB. */
-static void r4k_load_pgd(unsigned long pg_dir)
+void load_pgd(unsigned long pg_dir)
 {
 }
 
-static void r4k_pgd_init(unsigned long page)
+void pgd_init(unsigned long page)
 {
 	unsigned long *p = (unsigned long *) page;
 	int i;
@@ -2385,7 +2391,7 @@
  * updates the TLB with the new pte(s), and another which also checks
  * for the R4k "end of page" hardware bug and does the needy.
  */
-static void r4k_update_mmu_cache(struct vm_area_struct * vma,
+void update_mmu_cache(struct vm_area_struct * vma,
 				 unsigned long address, pte_t pte)
 {
 	unsigned long flags;
@@ -2394,7 +2400,7 @@
 	pte_t *ptep;
 	int idx, pid;
 
-	pid = (get_entryhi() & 0xff);
+	pid = get_entryhi() & 0xff;
 
 #ifdef DEBUG_TLB
 	if((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) {
@@ -2459,7 +2465,7 @@
 }
 #endif
 
-static void r4k_show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs * regs)
 {
 	/* Saved main processor registers. */
 	printk("$0 : %08lx %08lx %08lx %08lx\n",
@@ -2484,7 +2490,7 @@
 	       regs->cp0_epc, regs->cp0_status, regs->cp0_cause);
 }
 			
-static void r4k_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 				      unsigned long entryhi, unsigned long pagemask)
 {
         unsigned long flags;
@@ -2630,36 +2636,36 @@
 
 	switch(dc_lsize) {
 	case 16:
-		clear_page = r4k_clear_page_d16;
-		copy_page = r4k_copy_page_d16;
-		flush_cache_all = r4k_flush_cache_all_d16i16;
-		flush_cache_mm = r4k_flush_cache_mm_d16i16;
-		flush_cache_range = r4k_flush_cache_range_d16i16;
-		flush_cache_page = r4k_flush_cache_page_d16i16;
-		flush_page_to_ram = r4k_flush_page_to_ram_d16i16;
+		_clear_page = r4k_clear_page_d16;
+		_copy_page = r4k_copy_page_d16;
+		_flush_cache_all = r4k_flush_cache_all_d16i16;
+		_flush_cache_mm = r4k_flush_cache_mm_d16i16;
+		_flush_cache_range = r4k_flush_cache_range_d16i16;
+		_flush_cache_page = r4k_flush_cache_page_d16i16;
+		_flush_page_to_ram = r4k_flush_page_to_ram_d16i16;
 		break;
 	case 32:
 		prid = read_32bit_cp0_register(CP0_PRID) & 0xfff0;
 		if (prid == 0x2010) {			/* R4600 V1.7 */
-			clear_page = r4k_clear_page_r4600_v1;
-			copy_page = r4k_copy_page_r4600_v1;
+			_clear_page = r4k_clear_page_r4600_v1;
+			_copy_page = r4k_copy_page_r4600_v1;
 		} else if (prid == 0x2020) {		/* R4600 V2.0 */
-			clear_page = r4k_clear_page_r4600_v2;
-			copy_page = r4k_copy_page_r4600_v2;
+			_clear_page = r4k_clear_page_r4600_v2;
+			_copy_page = r4k_copy_page_r4600_v2;
 		} else {
-			clear_page = r4k_clear_page_d32;
-			copy_page = r4k_copy_page_d32;
+			_clear_page = r4k_clear_page_d32;
+			_copy_page = r4k_copy_page_d32;
 		}
-		flush_cache_all = r4k_flush_cache_all_d32i32;
-		flush_cache_mm = r4k_flush_cache_mm_d32i32;
-		flush_cache_range = r4k_flush_cache_range_d32i32;
-		flush_cache_page = r4k_flush_cache_page_d32i32;
-		flush_page_to_ram = r4k_flush_page_to_ram_d32i32;
+		_flush_cache_all = r4k_flush_cache_all_d32i32;
+		_flush_cache_mm = r4k_flush_cache_mm_d32i32;
+		_flush_cache_range = r4k_flush_cache_range_d32i32;
+		_flush_cache_page = r4k_flush_cache_page_d32i32;
+		_flush_page_to_ram = r4k_flush_page_to_ram_d32i32;
 		break;
 	}
-	dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc;
-	dma_cache_wback = r4k_dma_cache_wback;
-	dma_cache_inv = r4k_dma_cache_inv_pc;
+	_dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc;
+	_dma_cache_wback = r4k_dma_cache_wback;
+	_dma_cache_inv = r4k_dma_cache_inv_pc;
 }
 
 static void __init setup_scache_funcs(void)
@@ -2668,82 +2674,82 @@
 	case 16:
 		switch(dc_lsize) {
 		case 16:
-			flush_cache_all = r4k_flush_cache_all_s16d16i16;
-			flush_cache_mm = r4k_flush_cache_mm_s16d16i16;
-			flush_cache_range = r4k_flush_cache_range_s16d16i16;
-			flush_cache_page = r4k_flush_cache_page_s16d16i16;
-			flush_page_to_ram = r4k_flush_page_to_ram_s16d16i16;
+			_flush_cache_all = r4k_flush_cache_all_s16d16i16;
+			_flush_cache_mm = r4k_flush_cache_mm_s16d16i16;
+			_flush_cache_range = r4k_flush_cache_range_s16d16i16;
+			_flush_cache_page = r4k_flush_cache_page_s16d16i16;
+			_flush_page_to_ram = r4k_flush_page_to_ram_s16d16i16;
 			break;
 		case 32:
 			panic("Invalid cache configuration detected");
 		};
-		clear_page = r4k_clear_page_s16;
-		copy_page = r4k_copy_page_s16;
+		_clear_page = r4k_clear_page_s16;
+		_copy_page = r4k_copy_page_s16;
 		break;
 	case 32:
 		switch(dc_lsize) {
 		case 16:
-			flush_cache_all = r4k_flush_cache_all_s32d16i16;
-			flush_cache_mm = r4k_flush_cache_mm_s32d16i16;
-			flush_cache_range = r4k_flush_cache_range_s32d16i16;
-			flush_cache_page = r4k_flush_cache_page_s32d16i16;
-			flush_page_to_ram = r4k_flush_page_to_ram_s32d16i16;
+			_flush_cache_all = r4k_flush_cache_all_s32d16i16;
+			_flush_cache_mm = r4k_flush_cache_mm_s32d16i16;
+			_flush_cache_range = r4k_flush_cache_range_s32d16i16;
+			_flush_cache_page = r4k_flush_cache_page_s32d16i16;
+			_flush_page_to_ram = r4k_flush_page_to_ram_s32d16i16;
 			break;
 		case 32:
-			flush_cache_all = r4k_flush_cache_all_s32d32i32;
-			flush_cache_mm = r4k_flush_cache_mm_s32d32i32;
-			flush_cache_range = r4k_flush_cache_range_s32d32i32;
-			flush_cache_page = r4k_flush_cache_page_s32d32i32;
-			flush_page_to_ram = r4k_flush_page_to_ram_s32d32i32;
+			_flush_cache_all = r4k_flush_cache_all_s32d32i32;
+			_flush_cache_mm = r4k_flush_cache_mm_s32d32i32;
+			_flush_cache_range = r4k_flush_cache_range_s32d32i32;
+			_flush_cache_page = r4k_flush_cache_page_s32d32i32;
+			_flush_page_to_ram = r4k_flush_page_to_ram_s32d32i32;
 			break;
 		};
-		clear_page = r4k_clear_page_s32;
-		copy_page = r4k_copy_page_s32;
+		_clear_page = r4k_clear_page_s32;
+		_copy_page = r4k_copy_page_s32;
 		break;
 	case 64:
 		switch(dc_lsize) {
 		case 16:
-			flush_cache_all = r4k_flush_cache_all_s64d16i16;
-			flush_cache_mm = r4k_flush_cache_mm_s64d16i16;
-			flush_cache_range = r4k_flush_cache_range_s64d16i16;
-			flush_cache_page = r4k_flush_cache_page_s64d16i16;
-			flush_page_to_ram = r4k_flush_page_to_ram_s64d16i16;
+			_flush_cache_all = r4k_flush_cache_all_s64d16i16;
+			_flush_cache_mm = r4k_flush_cache_mm_s64d16i16;
+			_flush_cache_range = r4k_flush_cache_range_s64d16i16;
+			_flush_cache_page = r4k_flush_cache_page_s64d16i16;
+			_flush_page_to_ram = r4k_flush_page_to_ram_s64d16i16;
 			break;
 		case 32:
-			flush_cache_all = r4k_flush_cache_all_s64d32i32;
-			flush_cache_mm = r4k_flush_cache_mm_s64d32i32;
-			flush_cache_range = r4k_flush_cache_range_s64d32i32;
-			flush_cache_page = r4k_flush_cache_page_s64d32i32;
-			flush_page_to_ram = r4k_flush_page_to_ram_s64d32i32;
+			_flush_cache_all = r4k_flush_cache_all_s64d32i32;
+			_flush_cache_mm = r4k_flush_cache_mm_s64d32i32;
+			_flush_cache_range = r4k_flush_cache_range_s64d32i32;
+			_flush_cache_page = r4k_flush_cache_page_s64d32i32;
+			_flush_page_to_ram = r4k_flush_page_to_ram_s64d32i32;
 			break;
 		};
-		clear_page = r4k_clear_page_s64;
-		copy_page = r4k_copy_page_s64;
+		_clear_page = r4k_clear_page_s64;
+		_copy_page = r4k_copy_page_s64;
 		break;
 	case 128:
 		switch(dc_lsize) {
 		case 16:
-			flush_cache_all = r4k_flush_cache_all_s128d16i16;
-			flush_cache_mm = r4k_flush_cache_mm_s128d16i16;
-			flush_cache_range = r4k_flush_cache_range_s128d16i16;
-			flush_cache_page = r4k_flush_cache_page_s128d16i16;
-			flush_page_to_ram = r4k_flush_page_to_ram_s128d16i16;
+			_flush_cache_all = r4k_flush_cache_all_s128d16i16;
+			_flush_cache_mm = r4k_flush_cache_mm_s128d16i16;
+			_flush_cache_range = r4k_flush_cache_range_s128d16i16;
+			_flush_cache_page = r4k_flush_cache_page_s128d16i16;
+			_flush_page_to_ram = r4k_flush_page_to_ram_s128d16i16;
 			break;
 		case 32:
-			flush_cache_all = r4k_flush_cache_all_s128d32i32;
-			flush_cache_mm = r4k_flush_cache_mm_s128d32i32;
-			flush_cache_range = r4k_flush_cache_range_s128d32i32;
-			flush_cache_page = r4k_flush_cache_page_s128d32i32;
-			flush_page_to_ram = r4k_flush_page_to_ram_s128d32i32;
+			_flush_cache_all = r4k_flush_cache_all_s128d32i32;
+			_flush_cache_mm = r4k_flush_cache_mm_s128d32i32;
+			_flush_cache_range = r4k_flush_cache_range_s128d32i32;
+			_flush_cache_page = r4k_flush_cache_page_s128d32i32;
+			_flush_page_to_ram = r4k_flush_page_to_ram_s128d32i32;
 			break;
 		};
-		clear_page = r4k_clear_page_s128;
-		copy_page = r4k_copy_page_s128;
+		_clear_page = r4k_clear_page_s128;
+		_copy_page = r4k_copy_page_s128;
 		break;
 	}
-	dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc;
-	dma_cache_wback = r4k_dma_cache_wback;
-	dma_cache_inv = r4k_dma_cache_inv_sc;
+	_dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc;
+	_dma_cache_wback = r4k_dma_cache_wback;
+	_dma_cache_inv = r4k_dma_cache_inv_sc;
 }
 
 typedef int (*probe_func_t)(unsigned long);
@@ -2765,11 +2771,6 @@
 	setup_noscache_funcs();
 }
 
-static int r4k_user_mode(struct pt_regs *regs)
-{
-	return (regs->cp0_status & ST0_KSU) == KSU_USER;
-}
-
 void __init ld_mmu_r4xx0(void)
 {
 	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
@@ -2787,29 +2788,13 @@
 	case CPU_R4700:
 	case CPU_R5000:
 	case CPU_NEVADA:
-		flush_cache_page = r4k_flush_cache_page_d32i32_r4600;
+		_flush_cache_page = r4k_flush_cache_page_d32i32_r4600;
 	}
 
-	flush_cache_sigtramp = r4k_flush_cache_sigtramp;
+	_flush_cache_sigtramp = r4k_flush_cache_sigtramp;
 	if ((read_32bit_cp0_register(CP0_PRID) & 0xfff0) == 0x2020) {
-		flush_cache_sigtramp = r4600v20k_flush_cache_sigtramp;
+		_flush_cache_sigtramp = r4600v20k_flush_cache_sigtramp;
 	}
-
-	flush_tlb_all = r4k_flush_tlb_all;
-	flush_tlb_mm = r4k_flush_tlb_mm;
-	flush_tlb_range = r4k_flush_tlb_range;
-	flush_tlb_page = r4k_flush_tlb_page;
-	r4xx0_asid_setup();
-
-	load_pgd = r4k_load_pgd;
-	pgd_init = r4k_pgd_init;
-	update_mmu_cache = r4k_update_mmu_cache;
-
-	show_regs = r4k_show_regs;
-    
-        add_wired_entry = r4k_add_wired_entry;
-
-	user_mode = r4k_user_mode;
 
 	flush_cache_all();
 	write_32bit_cp0_register(CP0_WIRED, 0);