patch-2.4.20 linux-2.4.20/arch/mips/mm/c-mips32.c

• Lines: 110
• Date: Thu Nov 28 15:53:10 2002
• Orig file: linux-2.4.19/arch/mips/mm/c-mips32.c
• Orig date: Fri Aug 2 17:39:43 2002

diff -urN linux-2.4.19/arch/mips/mm/c-mips32.c linux-2.4.20/arch/mips/mm/c-mips32.c
@@ -424,33 +424,33 @@
 	unsigned int lsize;
 
         if (!(config & (1 << 31))) {
-	        /* 
-		 * Not a MIPS32 complainant CPU. 
+	        /*
+		 * Not a MIPS32 complainant CPU.
 		 * Config 1 register not supported, we assume R4k style.
 		 */
 	        icache_size = 1 << (12 + ((config >> 9) & 7));
 		ic_lsize = 16 << ((config >> 5) & 1);
 		mips_cpu.icache.linesz = ic_lsize;
-		
-		/* 
+
+		/*
 		 * We cannot infer associativity - assume direct map
 		 * unless probe template indicates otherwise
 		 */
 		if(!mips_cpu.icache.ways) mips_cpu.icache.ways = 1;
-		mips_cpu.icache.sets = 
+		mips_cpu.icache.sets =
 			(icache_size / ic_lsize) / mips_cpu.icache.ways;
 	} else {
-	       config1 = read_mips32_cp0_config1(); 
+	       config1 = read_mips32_cp0_config1();
 
 	       if ((lsize = ((config1 >> 19) & 7)))
 		       mips_cpu.icache.linesz = 2 << lsize;
-	       else 
+	       else
 		       mips_cpu.icache.linesz = lsize;
 	       mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7);
 	       mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7);
 
 	       ic_lsize = mips_cpu.icache.linesz;
-	       icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways * 
+	       icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways *
 		             ic_lsize;
 	}
 	printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n",
@@ -463,32 +463,32 @@
 	unsigned int lsize;
 
         if (!(config & (1 << 31))) {
-	        /* 
-		 * Not a MIPS32 complainant CPU. 
+	        /*
+		 * Not a MIPS32 complainant CPU.
 		 * Config 1 register not supported, we assume R4k style.
-		 */  
+		 */
 		dcache_size = 1 << (12 + ((config >> 6) & 7));
 		dc_lsize = 16 << ((config >> 4) & 1);
 		mips_cpu.dcache.linesz = dc_lsize;
-		/* 
+		/*
 		 * We cannot infer associativity - assume direct map
 		 * unless probe template indicates otherwise
 		 */
 		if(!mips_cpu.dcache.ways) mips_cpu.dcache.ways = 1;
-		mips_cpu.dcache.sets = 
+		mips_cpu.dcache.sets =
 			(dcache_size / dc_lsize) / mips_cpu.dcache.ways;
 	} else {
 	        config1 = read_mips32_cp0_config1();
 
 		if ((lsize = ((config1 >> 10) & 7)))
 		        mips_cpu.dcache.linesz = 2 << lsize;
-		else 
+		else
 		        mips_cpu.dcache.linesz= lsize;
 		mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7);
 		mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7);
 
 		dc_lsize = mips_cpu.dcache.linesz;
-		dcache_size = 
+		dcache_size =
 			mips_cpu.dcache.sets * mips_cpu.dcache.ways
 			* dc_lsize;
 	}
@@ -638,12 +638,12 @@
 
 	if (sc_present) {
 	  	mips_cpu.scache.linesz = sc_lsize;
-		/* 
+		/*
 		 * We cannot infer associativity - assume direct map
 		 * unless probe template indicates otherwise
 		 */
 		if(!mips_cpu.scache.ways) mips_cpu.scache.ways = 1;
-		mips_cpu.scache.sets = 
+		mips_cpu.scache.sets =
 		  (scache_size / sc_lsize) / mips_cpu.scache.ways;
 
 		setup_scache_funcs();
@@ -657,11 +657,7 @@
 {
 	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
 
-#ifdef CONFIG_MIPS_UNCACHED
-	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-#else
-	change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
-#endif
+	change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
 
 	probe_icache(config);
 	probe_dcache(config);