patch-2.4.27 linux-2.4.27/drivers/message/fusion/lsi/mpi_cnfg.h
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- Lines: 748
- Date:
2004-08-07 16:26:04.904357050 -0700
- Orig file:
linux-2.4.26/drivers/message/fusion/lsi/mpi_cnfg.h
- Orig date:
2004-02-18 05:36:31.000000000 -0800
diff -urN linux-2.4.26/drivers/message/fusion/lsi/mpi_cnfg.h linux-2.4.27/drivers/message/fusion/lsi/mpi_cnfg.h
@@ -2,11 +2,11 @@
* Copyright (c) 2000-2003 LSI Logic Corporation.
*
*
- * Name: MPI_CNFG.H
+ * Name: mpi_cnfg.h
* Title: MPI Config message, structures, and Pages
* Creation Date: July 27, 2000
*
- * MPI_CNFG.H Version: 01.02.12
+ * mpi_cnfg.h Version: 01.05.xx
*
* Version History
* ---------------
@@ -176,6 +176,19 @@
} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
+typedef struct _CONFIG_EXTENDED_PAGE_HEADER
+{
+ U8 PageVersion; /* 00h */
+ U8 Reserved1; /* 01h */
+ U8 PageNumber; /* 02h */
+ U8 PageType; /* 03h */
+ U16 ExtPageLength; /* 04h */
+ U8 ExtPageType; /* 06h */
+ U8 Reserved2; /* 07h */
+} fCONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
+ ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
+
+
/****************************************************************************
* PageType field values
@@ -197,12 +210,23 @@
#define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
#define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
+#define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
+#define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
#define MPI_CONFIG_PAGETYPE_MASK (0x0F)
#define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
/****************************************************************************
+* ExtPageType field values
+****************************************************************************/
+#define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
+#define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
+#define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
+#define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
+
+
+/****************************************************************************
* PageAddress field values
****************************************************************************/
#define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
@@ -236,6 +260,24 @@
#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
+#define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
+#define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
+#define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
+#define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
+#define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
+#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
+#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
+#define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
+#define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
+#define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
+#define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
+#define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
+#define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
+
+#define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x00FF0000)
+#define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (16)
+#define MPI_SAS_PHY_PGAD_DEVHANDLE_MASK (0x0000FFFF)
+#define MPI_SAS_PHY_PGAD_DEVHANDLE_SHIFT (0)
/****************************************************************************
@@ -247,7 +289,8 @@
U8 Reserved; /* 01h */
U8 ChainOffset; /* 02h */
U8 Function; /* 03h */
- U8 Reserved1[3]; /* 04h */
+ U16 ExtPageLength; /* 04h */
+ U8 ExtPageType; /* 06h */
U8 MsgFlags; /* 07h */
U32 MsgContext; /* 08h */
U8 Reserved2[8]; /* 0Ch */
@@ -277,7 +320,8 @@
U8 Reserved; /* 01h */
U8 MsgLength; /* 02h */
U8 Function; /* 03h */
- U8 Reserved1[3]; /* 04h */
+ U16 ExtPageLength; /* 04h */
+ U8 ExtPageType; /* 06h */
U8 MsgFlags; /* 07h */
U32 MsgContext; /* 08h */
U8 Reserved2[2]; /* 0Ch */
@@ -299,29 +343,21 @@
* Manufacturing Config pages
****************************************************************************/
#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
-#define MPI_MANUFACTPAGE_VENDORID_TREBIA (0x1783)
-
+/* Fibre Channel */
#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
-
+/* SCSI */
#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
-
-#define MPI_MANUFACTPAGE_DEVID_SA2010 (0x0804)
-#define MPI_MANUFACTPAGE_DEVID_SA2010ZC (0x0805)
-#define MPI_MANUFACTPAGE_DEVID_SA2020 (0x0806)
-#define MPI_MANUFACTPAGE_DEVID_SA2020ZC (0x0807)
-
-#define MPI_MANUFACTPAGE_DEVID_SNP1000 (0x0010)
-#define MPI_MANUFACTPAGE_DEVID_SNP500 (0x0020)
-
+/* SAS */
+#define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
typedef struct _CONFIG_PAGE_MANUFACTURING_0
@@ -405,8 +441,8 @@
U8 InfoOffset1; /* 0Ah */
U8 InfoSize1; /* 0Bh */
U8 InquirySize; /* 0Ch */
- U8 Reserved2; /* 0Dh */
- U16 Reserved3; /* 0Eh */
+ U8 Flags; /* 0Dh */
+ U16 Reserved2; /* 0Eh */
U8 InquiryData[56]; /* 10h */
U32 ISVolumeSettings; /* 48h */
U32 IMEVolumeSettings; /* 4Ch */
@@ -414,7 +450,30 @@
} fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
-#define MPI_MANUFACTURING4_PAGEVERSION (0x00)
+#define MPI_MANUFACTURING4_PAGEVERSION (0x01)
+
+/* defines for the Flags field */
+#define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
+
+
+typedef struct _CONFIG_PAGE_MANUFACTURING_5
+{
+ fCONFIG_PAGE_HEADER Header; /* 00h */
+ U64 BaseWWID; /* 04h */
+} fCONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
+ ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
+
+#define MPI_MANUFACTURING5_PAGEVERSION (0x00)
+
+
+typedef struct _CONFIG_PAGE_MANUFACTURING_6
+{
+ fCONFIG_PAGE_HEADER Header; /* 00h */
+ U32 ProductSpecificInfo;/* 04h */
+} fCONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
+ ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
+
+#define MPI_MANUFACTURING6_PAGEVERSION (0x00)
/****************************************************************************
@@ -438,17 +497,18 @@
} fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
-#define MPI_IOUNITPAGE1_PAGEVERSION (0x00)
+#define MPI_IOUNITPAGE1_PAGEVERSION (0x01)
/* IO Unit Page 1 Flags defines */
-
#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
+#define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
+#define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
typedef struct _MPI_ADAPTER_INFO
@@ -478,6 +538,11 @@
#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
+#define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
+#define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
+#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
+#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
+
/*
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
@@ -540,6 +605,12 @@
#define MPI_IOCPAGE1_PAGEVERSION (0x01)
+/* defines for the Flags field */
+#define MPI_IOCPAGE1_EEDP_HOST_SUPPORTS_DIF (0x08000000)
+#define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
+#define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
+#define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
+#define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
@@ -680,7 +751,7 @@
typedef struct _CONFIG_PAGE_IOC_5
{
- fCONFIG_PAGE_HEADER Header; /* 00h */
+ fCONFIG_PAGE_HEADER Header; /* 00h */
U32 Reserved1; /* 04h */
U8 NumHotSpares; /* 08h */
U8 Reserved2; /* 09h */
@@ -692,6 +763,57 @@
#define MPI_IOCPAGE5_PAGEVERSION (0x00)
+/****************************************************************************
+* BIOS Port Config Pages
+****************************************************************************/
+
+typedef struct _CONFIG_PAGE_BIOS_1
+{
+ fCONFIG_PAGE_HEADER Header; /* 00h */
+ U32 BiosOptions; /* 04h */
+ U32 IOCSettings; /* 08h */
+ U32 Reserved1; /* 0Ch */
+ U32 DeviceSettings; /* 10h */
+ U16 NumberOfDevices; /* 14h */
+ U16 Reserved2; /* 16h */
+ U16 IOTimeoutBlockDevicesNonRM; /* 18h */
+ U16 IOTimeoutSequential; /* 1Ah */
+ U16 IOTimeoutOther; /* 1Ch */
+ U16 IOTimeoutBlockDevicesRM; /* 1Eh */
+} fCONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
+ BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
+
+#define MPI_BIOSPAGE1_PAGEVERSION (0x00)
+
+/* values for the BiosOptions field */
+#define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
+#define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
+#define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
+#define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
+
+/* values for the IOCSettings field */
+#define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
+#define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
+
+#define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
+#define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
+#define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
+#define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
+
+#define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
+#define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
+#define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
+#define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
+#define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
+
+#define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
+
+/* values for the DeviceSettings field */
+#define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
+#define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
+#define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
+#define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
+
/****************************************************************************
* SCSI Port Config Pages
@@ -711,7 +833,27 @@
#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
+#define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
+#define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
+#define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
+#define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
+#define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
+#define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
+#define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
+#define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
+#define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
+
+#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
+#define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
+ ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MIN_SYNC_PERIOD) \
+ >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
+ )
#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
+#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
+#define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
+ ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MAX_SYNC_OFFSET) \
+ >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
+ )
#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
@@ -736,11 +878,12 @@
} fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
-#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02)
+#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
/* Configuration values */
#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
+#define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
/* TargetConfig values */
#define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
@@ -777,6 +920,7 @@
#define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
#define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
+
/* PortSettings values */
#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
@@ -785,7 +929,11 @@
#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
+#define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
+#define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
+#define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
+#define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
@@ -822,7 +970,9 @@
#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
+#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
+#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
@@ -852,7 +1002,9 @@
#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
+#define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
+#define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
@@ -998,13 +1150,19 @@
#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
-#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
-#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
-#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
+#define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
+#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
+#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
+#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
+#define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
+#define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
+#define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
+#define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
+
typedef struct _CONFIG_PAGE_FC_PORT_1
@@ -1019,11 +1177,12 @@
U8 AltConnector; /* 1Bh */
U8 NumRequestedAliases; /* 1Ch */
U8 RR_TOV; /* 1Dh */
- U16 Reserved2; /* 1Eh */
+ U8 InitiatorDeviceTimeout; /* 1Eh */
+ U8 InitiatorIoPendTimeout; /* 1Fh */
} fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
-#define MPI_FCPORTPAGE1_PAGEVERSION (0x05)
+#define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
@@ -1031,6 +1190,7 @@
#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
#define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
+#define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
#define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
#define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
@@ -1066,6 +1226,8 @@
#define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
+#define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
+
typedef struct _CONFIG_PAGE_FC_PORT_2
{
@@ -1627,5 +1789,317 @@
#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
+
+/****************************************************************************
+* Inband Config Pages
+****************************************************************************/
+
+typedef struct _CONFIG_PAGE_INBAND_0
+{
+ fCONFIG_PAGE_HEADER Header; /* 00h */
+ MPI_VERSION_FORMAT InbandVersion; /* 04h */
+ U16 MaximumBuffers; /* 08h */
+ U16 Reserved1; /* 0Ah */
+} fCONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
+ InbandPage0_t, MPI_POINTER pInbandPage0_t;
+
+#define MPI_INBAND_PAGEVERSION (0x00)
+
+
+
+/****************************************************************************
+* SAS IO Unit Config Pages
+****************************************************************************/
+
+typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
+{
+ U8 Port; /* 00h */
+ U8 PortFlags; /* 01h */
+ U8 PhyFlags; /* 02h */
+ U8 NegotiatedLinkRate; /* 03h */
+ U32 ControllerPhyDeviceInfo;/* 04h */
+ U16 AttachedDeviceHandle; /* 08h */
+ U16 ControllerDevHandle; /* 0Ah */
+ U32 Reserved2; /* 0Ch */
+} MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
+ SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
+
+/*
+ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
+ * one and check Header.PageLength at runtime.
+ */
+#ifndef MPI_SAS_IOUNIT0_PHY_MAX
+#define MPI_SAS_IOUNIT0_PHY_MAX (1)
+#endif
+
+typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U8 NumPhys; /* 0Ch */
+ U8 Reserved2; /* 0Dh */
+ U16 Reserved3; /* 0Eh */
+ MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
+} fCONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
+ SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
+
+#define MPI_SASIOUNITPAGE0_PAGEVERSION (0x00)
+
+/* values for SAS IO Unit Page 0 PortFlags */
+#define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
+#define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
+#define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
+#define MPI_SAS_IOUNIT0_PORT_FLAGS_WAIT_FOR_PORTENABLE (0x02)
+#define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
+
+/* values for SAS IO Unit Page 0 PhyFlags */
+#define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
+#define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
+#define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
+
+/* values for SAS IO Unit Page 0 NegotiatedLinkRate */
+#define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
+#define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
+#define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
+#define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
+#define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
+#define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
+
+/* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
+
+
+typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
+{
+ U8 Port; /* 00h */
+ U8 PortFlags; /* 01h */
+ U8 PhyFlags; /* 02h */
+ U8 MaxMinLinkRate; /* 03h */
+ U32 ControllerPhyDeviceInfo;/* 04h */
+ U32 Reserved1; /* 08h */
+} MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
+ SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
+
+/*
+ * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
+ * one and check Header.PageLength at runtime.
+ */
+#ifndef MPI_SAS_IOUNIT1_PHY_MAX
+#define MPI_SAS_IOUNIT1_PHY_MAX (1)
+#endif
+
+typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U8 NumPhys; /* 0Ch */
+ U8 Reserved2; /* 0Dh */
+ U16 Reserved3; /* 0Eh */
+ MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 10h */
+} fCONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
+ SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
+
+#define MPI_SASIOUNITPAGE1_PAGEVERSION (0x00)
+
+/* values for SAS IO Unit Page 0 PortFlags */
+#define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
+#define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
+#define MPI_SAS_IOUNIT1_PORT_FLAGS_WAIT_FOR_PORTENABLE (0x02)
+#define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
+
+/* values for SAS IO Unit Page 0 PhyFlags */
+#define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
+#define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
+#define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
+
+/* values for SAS IO Unit Page 0 MaxMinLinkRate */
+#define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
+#define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
+#define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
+#define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
+#define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
+#define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
+
+/* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
+
+
+typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U16 MaxPersistentIDs; /* 0Ch */
+ U16 NumPersistentIDsUsed; /* 0Eh */
+ U8 Status; /* 10h */
+ U8 Flags; /* 11h */
+ U16 Reserved2; /* 12h */
+} fCONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
+ SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
+
+#define MPI_SASIOUNITPAGE2_PAGEVERSION (0x00)
+
+/* values for SAS IO Unit Page 2 Status field */
+#define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
+#define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
+
+/* values for SAS IO Unit Page 2 Flags field */
+#define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
+
+
+typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U32 MaxInvalidDwordCount; /* 0Ch */
+ U32 InvalidDwordCountTime; /* 10h */
+ U32 MaxRunningDisparityErrorCount; /* 14h */
+ U32 RunningDisparityErrorTime; /* 18h */
+ U32 MaxLossDwordSynchCount; /* 1Ch */
+ U32 LossDwordSynchCountTime; /* 20h */
+ U32 MaxPhyResetProblemCount; /* 24h */
+ U32 PhyResetProblemTime; /* 28h */
+} fCONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
+ SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
+
+#define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
+
+
+typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U64 SASAddress; /* 0Ch */
+ U32 Reserved2; /* 14h */
+ U16 DevHandle; /* 18h */
+ U16 ParentDevHandle; /* 1Ah */
+ U16 ExpanderChangeCount; /* 1Ch */
+ U16 ExpanderRouteIndexes; /* 1Eh */
+ U8 NumPhys; /* 20h */
+ U8 SASLevel; /* 21h */
+ U8 Flags; /* 22h */
+ U8 Reserved3; /* 23h */
+} fCONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
+ SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
+
+#define MPI_SASEXPANDER0_PAGEVERSION (0x00)
+
+/* values for SAS Expander Page 0 Flags field */
+#define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
+#define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
+
+
+typedef struct _CONFIG_PAGE_SAS_DEVICE_0
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U64 SASAddress; /* 0Ch */
+ U32 Reserved2; /* 14h */
+ U16 DevHandle; /* 18h */
+ U8 TargetID; /* 1Ah */
+ U8 Bus; /* 1Bh */
+ U32 DeviceInfo; /* 1Ch */
+ U16 Flags; /* 20h */
+ U8 PhysicalPort; /* 22h */
+ U8 Reserved3; /* 23h */
+} fCONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
+ SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
+
+#define MPI_SASDEVICE0_PAGEVERSION (0x00)
+
+/* values for SAS Device Page 0 Flags field */
+#define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x04)
+#define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x02)
+#define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x01)
+
+/* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
+
+
+typedef struct _CONFIG_PAGE_SAS_DEVICE_1
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U64 SASAddress; /* 0Ch */
+ U32 Reserved2; /* 14h */
+ U16 DevHandle; /* 18h */
+ U8 TargetID; /* 1Ah */
+ U8 Bus; /* 1Bh */
+ U8 InitialRegDeviceFIS[20];/* 1Ch */
+} fCONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
+ SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
+
+#define MPI_SASDEVICE1_PAGEVERSION (0x00)
+
+
+typedef struct _CONFIG_PAGE_SAS_PHY_0
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U64 SASAddress; /* 0Ch */
+ U16 AttachedDevHandle; /* 14h */
+ U8 AttachedPhyIdentifier; /* 16h */
+ U8 Reserved2; /* 17h */
+ U32 AttachedDeviceInfo; /* 18h */
+ U8 ProgrammedLinkRate; /* 20h */
+ U8 HwLinkRate; /* 21h */
+ U8 ChangeCount; /* 22h */
+ U8 Reserved3; /* 23h */
+ U32 PhyInfo; /* 24h */
+} fCONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
+ SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
+
+#define MPI_SASPHY0_PAGEVERSION (0x00)
+
+/* values for SAS PHY Page 0 ProgrammedLinkRate field */
+#define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
+#define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
+#define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
+#define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
+#define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
+#define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
+#define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
+#define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
+
+/* values for SAS PHY Page 0 HwLinkRate field */
+#define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
+#define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
+#define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
+#define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
+#define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
+#define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
+
+/* values for SAS PHY Page 0 PhyInfo field */
+#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
+#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
+#define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
+
+#define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
+#define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
+
+#define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
+#define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
+#define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
+#define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
+
+#define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
+#define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
+#define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
+#define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
+#define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
+#define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
+#define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
+
+
+typedef struct _CONFIG_PAGE_SAS_PHY_1
+{
+ fCONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
+ U32 Reserved1; /* 08h */
+ U32 InvalidDwordCount; /* 0Ch */
+ U32 RunningDisparityErrorCount; /* 10h */
+ U32 LossDwordSynchCount; /* 14h */
+ U32 PhyResetProblemCount; /* 18h */
+} fCONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
+ SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
+
+#define MPI_SASPHY1_PAGEVERSION (0x00)
+
+
#endif
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)